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low cost, dual, high current output line driver with shutdown ada4311-1 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features high speed ?3 db bandwidth: 310 mhz, g = +5, r load = 50 slew rate: 1050 v/s, r load = 50 wide output swing 20.6 v p-p differential, r load of 100 from 12 v supply high output current low distortion ?98 dbc typical at 1 mhz, v out = 2 v p-p, g = +5, r load = 100 ?72 dbc typical at 10 mhz, v out = 2 v p-p, g = +5, r load = 100 power management and shutdown control inputs cmos level compatible shutdown quiescent current: 1 ma/amplifier selectable quiescent current: 1 ma to 11.8 ma/amplifier applications home networking line drivers twisted pair line drivers power line communications (plc) video line drivers arb line drivers i/q channel amplifiers pin configuration nc = no connect +v s 1 nc 2 out a 3 ?in a 4 +in a 5 out b 10 ?in b 9 +in b 8 pd1 7 pd0 6 a da4311-1 06940-001 figure 1. thermally enhanced, 10-lead mini_so_ep typical application v mid * ada4311-1 ada4311-1 1/2 1/2 *v mid = v cc ? gnd 2 06940-002 figure 2. typical plc driver application general description the ada4311-1 is comprised of two high speed, current feedback operational amplifiers. the high output current, high bandwidth, and fast slew rate make it an excellent choice for broadband applications requiring high linearity performance while driving low impedance loads. the ada4311-1 incorporates a power management function that provides shutdown capabilities and the ability to optimize the quiescent current of the amplifiers. the cmos-compatible, power-down control pins (pd1 and pd0) enable the ada4311-1 to operate in four different modes: full power, medium power, low power, and complete power-down. in power-down mode, the quiescent current drops to only 1.0 ma/amplifier, while the outputs go to a high impedance state. the ada4311-1 is available in a thermally enhanced, 10-lead msop with an exposed paddle for improved thermal conduction. the ada4311-1 is rated to work in the extended industrial temperature range of ?40c to +85c.
ada4311-1 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configuration ............................................................................. 1 typical application ........................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 application information ................................................................ 11 feedback resistor selection ...................................................... 11 power control modes of operation ........................................ 11 exposed thermal pad connections ........................................ 11 powerline application ............................................................... 11 board layout ............................................................................... 12 power supply bypassing ............................................................ 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 8/07revision 0: initial version
ada4311-1 rev. 0 | page 3 of 16 specifications v s = 12 v, r f = 499 (@ t a = 25c, g = +5, r l = 100 to v s /2), unless otherwise noted. table 1. parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth v out = 0.1 v p-p, pd1 = 0, pd0 = 0, r load = 50 310 mhz v out = 0.1 v p-p, pd1 = 0, pd0 = 1, r load = 50 220 mhz v out = 0.1 v p-p, pd1 = 1, pd0 = 0, r load = 50 140 mhz full power bandwidth v out = 10.2 v p-p, pd1 = 0, pd0 = 0, r load = 50 12.9 mhz slew rate v out = 2 v p-p, pd1 = 0, pd0 = 0 1050 v/s v out = 2 v p-p, pd1 = 0, pd0 = 1 1050 v/s v out = 2 v p-p, pd1 = 1, pd0 = 0 1000 v/s noise/distortion performance differential distortion (worst harmonic) f c = 1 mhz, v out = 2 v p-p pd1 = 0, pd0 = 0 ?98 dbc pd1 = 0, pd0 = 1 ?95 dbc pd1 = 1, pd0 = 0 ?86 dbc f c = 10 mhz, v out = 2 v p-p pd1 = 0, pd0 = 0 ?72 dbc pd1 = 0, pd0 = 1 ?63 dbc pd1 = 1, pd0 = 0 ?52 dbc f c = 20 mhz, v out = 2 v p-p pd1 = 0, pd0 = 0 ?56 dbc pd1 = 0, pd0 = 1 ?49 dbc pd1 = 1, pd0 = 0 ?43 dbc input voltage noise f = 100 khz 2.4 nv/hz input current noise f = 100 khz 17 pa/hz dc performance input offset voltage ?3 +1 +3 mv input bias current noninverting input ?9 ?2 +3 a inverting input ?4 +4.5 +16 a open-loop transimpedance r load = 50 4 14 m r load = 100 15 35 m common-mode rejection 57 62 db input characteristics input resistance +in, f < 100 khz 500 k output characteristics single-ended, +swing r load = 50 11 11.1 v p single-ended, ?swing r load = 50 0.9 1 v p single-ended, +swing r load = 100 11 11.1 v p single-ended, ?swing r load = 100 0.8 0.9 v p differential swing r load = 100 20.2 20.6 v p-p power supply single supply 12 v supply current pd1 = 0, pd0 = 0 10.5 11.8 13 ma/amp pd1 = 0, pd0 = 1 7 7.9 9 ma/amp pd1 = 1, pd0 = 0 4.3 5.2 6.3 ma/amp pd1 = 1, pd0 = 1 0.9 1.3 ma/amp
ada4311-1 rev. 0 | page 4 of 16 parameter test conditions/comments min typ max unit power-down pins pd1, pd0 threshold referenced to gnd 1.5 v high level input voltage, v ih 2 5 v low level input voltage, v il 0 0.8 v pd1, pd0 = 0 pin bias current pd1 or pd0 = 0 v ?1.5 ?0.2 +1.5 a pd1, pd0 = 1 pin bias current pd1 or pd0 = 3 v 40 63 80 a enable/disable time 130/116 ns power supply rejection ratio ?63 ?70 db
ada4311-1 rev. 0 | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltage 13.6 v power dissipation (t jmax ? t a )/ ja storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance thermal resistance ( ja ) is specified for the worst-case conditions, that is, ja is specified for device soldered in circuit board for surface-mount packages. table 3. package type ja unit 10-lead mini_so_ep 44 c/w maximum power dissipation the maximum safe power dissipation for the ada4311-1 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. exceeding a junction temperature of 150c for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 10-lead mini_so_ep (44c/w) on a jedec standard 4-layer board. ja values are approximations. ambient temperature (c) maximum power dissipation (w) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?35 ?15 5 25 45 65 85 mini_so_ep-10 06940-003 figure 3. maximum power dissipation vs. temperature for a 4-layer board esd caution
ada4311-1 rev. 0 | page 6 of 16 pin configuration and fu nction descriptions nc = no connect +v s 1 nc 2 out a 3 ?in a 4 +in a 5 out b 10 ?in b 9 +in b 8 pd1 7 pd0 6 a da4311-1 06940-004 figure 4. pin configuration table 4. pin function description pin no. mnemonic description 1 +v s positive power supply input. 2 nc no connection. 3 out a amplifier a output. 4 ?in a amplifier a inverting input. 5 +in a amplifier a noninverting input. 6 pd0 power dissipation control. 7 pd1 power dissipation control. 8 +in b amplifier b noninverting input. 9 ?in b amplifier b inverting input. 10 out b amplifier b output. 11 (exposed paddle) gnd ground (electrical connection required).
ada4311-1 rev. 0 | page 7 of 16 typical performance characteristics ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 1 10 100 1000 g = +5 g = +10 g = +20 frequency (mhz) normalized gain (db) v out = 100mv p-p r l = 50 ? pd1, pd0 = 0, 0 06940-005 figure 5. small signal frequency response for various closed-loop gains 1 10 100 1000 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 frequency (mhz) gain (db) v out = 100mv p-p r l = 50 ? g = +5 pd1, pd0 = 0, 0 pd1, pd0 = 0, 1 pd1, pd0 = 1, 0 06940-006 figure 6. small signal frequency response for various modes output (v) ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 g = +5 r l = 50 ? 10ns/div 06940-010 figure 7. small signal transient response ?120 ?50 frequency (mhz) harmonic distortion (dbc) ?130 ?100 ?90 ?80 ?70 ?60 ? 40 0.1 11 0 ?110 1 0 0 v out = 2v p-p r l = 100 ? g = +5 pd1, pd0 = 0, 0 pd1, pd0 = 0, 1 pd1, pd0 = 1, 0 hd2 hd3 06940-008 figure 8. differential harmonic distortion vs. frequency 06940-021 output voltage (v p-p) harmonic distortion (dbc) ?120 ?110 ?100 ?90 ?80 ?70 ? 60 0.1 1 10 hd2 hd3 f = 5mhz r l = 100 ? g = +5 figure 9. differential harmonic distortion vs. output voltage 06940-022 load resistance ( ? ) harmonic distortion (dbc) 10 100 1000 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 hd2 hd3 v out = 2v p-p f = 5mhz g = +5 figure 10. differential harmonic distortion vs. load resistance
ada4311-1 rev. 0 | page 8 of 16 frequency (hz) transimpedance ( ? ) phase (degrees) 100 1k 10k 100k 1m 10m 100m 1g ?270 ?225 ?180 ?135 ?90 ?45 0 r l = 100 ? 06940-007 100 1k 10k 100k 1m 10m 100m magnitude phase figure 11. open-loop transimpedance and phase vs. frequency common-mode rejection (db) ?70 ?50 ?40 ?30 ?20 0 ?60 ?10 frequency (mhz) 0.01 0.1 1 10 100 1000 pd1, pd0 = 0, 0 r l = 100 ? 0 6940-011 figure 12. common-mode rejection vs. frequency ?70 ?50 ?40 ?30 ? 10 ?60 ?20 +psr frequency (mhz) power supply rejection (db) 0.01 0.1 1 10 100 1000 pd1, pd0 = 0, 0 r l = 100 ? 06940-012 figure 13. power supply rejection vs. frequency frequency (mhz) output impedance ( ? ) 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 pd1, pd0 = 0, 0 0 6940-013 figure 14. closed-loop outp ut impedance vs. frequency 06940-015 frequency (mhz) output impedance ( ? ) 1 10 100 1k 10k 100k 1m 0.01 0.1 1 10 100 1000 pd1, pd0 = 1, 1 figure 15. output impedanc e vs. frequency (disabled) 0 6940-009 frequency (hz) voltage noise (nv/ hz) 1 10 100 10 100 1k 10k 100k 1m 10m 100m 1g figure 16. voltage noise vs. frequency
ada4311-1 rev. 0 | page 9 of 16 frequency (mhz) feedthrough (db) ?100 ?80 ?60 ?40 ? 20 10 1 100 1000 pd1, pd0 = 1, 1 06940-014 figure 17. feedthrough vs. frequency 06940-016 voltage (v) 8 v out 0 1 2 3 4 5 6 7 v pd1 , v pd0 time (1 s/div) 0123456 figure 18. power-down turn on/turn off frequency (hz) ?100 ?80 ?60 ?40 0 crosstalk (db) ?20 0.1 1 10 100 1000 06940-017 figure 19. crosstalk vs. frequency 06940-020 load ( ? ) v out (p-p) 6 7 8 9 10 11 12 30 100 1000 figure 20. single-ended output swing vs. load
ada4311-1 rev. 0 | page 10 of 16 theory of operation the ada4311-1 is a dual-current feedback amplifier with high output current capability. with a current feedback amplifier, the current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance, dv o /di in or t z . the open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. figure 21 shows a simplified model of a current feedback amplifier. because r in is proportional to 1/g m , the equivalent voltage gain is t z g m , where g m is the transconductance of the input stage. basic analysis of the follower with gain circuit yields () () fin z z in out rrgst st g v v ++ = where: g f r r g += 1 50 1 = m in g r because g r in << r f for low gains, a current feedback amplifier has relatively constant bandwidth vs. gain, the 3 db point being set when |t z | = r f . for a real amplifier, there are additional poles that contribute excess phase, and there is a value for r f below which the amplifier is unstable. tolerance for peaking and desired flatness determines the optimum r f in each application. r f v out r g r n v in r in i in t z 0 6940-018 figure 21. simplified block diagram
ada4311-1 rev. 0 | page 11 of 16 application information feedback resistor selection the feedback resistor has a direct impact on the closed-loop bandwidth and stability of the current feedback op amp. reducing the resistance below the recommended value can make the amplifier response peak and even become unstable. increasing the size of the feedback resistor beyond the recom- mended value reduces the closed-loop bandwidth. tabl e 5 provides a convenient reference for quickly determining the feedback and gain resistor values, and the corresponding bandwidth, for common gain configurations. the recommended feedback resistor value for the ada4311-1 is 499 . table 5. recommended values and frequency performance 1 gain r f () r g () ?3 db ss bw (mhz) +5 499 124 310 +5 1 k 250 220 +10 499 55.4 175 +20 499 26.1 84 1 conditions: v s = 12 v, t a = 25c, r l = 50 , pd1, pd0 = 0, 0. power control modes of operation the ada4311-1 features four power modes: full power, ? power, ? power, and shutdown. the power modes are controlled by two logic pins, pd0 and pd1. the power-down control pins are compatible with standard 3 v and 5 v cmos logic. table 6 shows the various power modes and associated logic states. in the power-down mode, the output of the amplifier goes into a high impedance state. table 6. power modes pd1 pd0 power mode total supply current (ma) output impedance low low full power 23.6 low low high ? power 15.8 low high low ? power 10.4 low high high power-down 1.8 high exposed thermal pad connections the exposed thermal pad on the 10-lead msop is both the reference for the pd pins and the only electrical connection for the negative supply voltage. therefore, in the 10-lead msop, the ada4311-1 can only be used on a single supply. the exposed thermal pad must be connected to ground. failure to do so renders the part inoperable. a requirement for this package is that the thermal pad be connected to a solid plane with low thermal resistance, ensuring adequate heat transfer away from the die and into the board. powerline application applications (that is, powerline av modems) requiring greater than 10 dbm peak power should consider using an external line driver, such as the ada4311-1. figure 22 shows an example interface between the txdac? output and the ada4311-1 biased for single-supply operation. the peak-to-peak differential output voltage swing of the txdac should be limited to 2 v p-p, with the gain of the ada4311-1 configured to realize the additional voltage gain required by the application. a low- pass filter should be considered to filter the dac images inherent in the signal reconstruction process. in addition, dc blocking capacitors are required to level-shift the output signal of the txdac to the common-mode level of the ada4311-1 (that is, v mid = v cc ? gnd/2). 0.1f r set r e f i o ioutp+ ioutp? 0db to ?7.5db optional lclpf v mid t x d i s a b l e ada4311-1 ada4311-1 1/2 1/2 refadj txdac 06940-019 figure 22. txdac output directly via center-tap transformer
ada4311-1 rev. 0 | page 12 of 16 board layout as is the case with all high speed applications, careful attention to printed circuit board (pcb) layout details prevents associated board parasitics from becoming problematic. proper rf design technique is mandatory. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low impedance return path. removing the ground plane on all layers from the area near the input and output pins reduces stray capacitance, particularly in the area of the inverting inputs. signal lines connecting the feedback and gain resistors should be as short as possible to minimize the inductance and stray capacitance associated with these traces. termination resistors and loads should be located as close as possible to their respective inputs and outputs. input and output traces should be kept as far apart as possible to minimize coupling (crosstalk) though the board. wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize balanced performance. when running differential signals over a long distance, the traces on the pcb should be close. doing this reduces the radiated energy and makes the circuit less susceptible to rf interference. adherence to stripline design techniques for long signal traces (greater than about 1 inch) is recommended. for more information on high speed board layout, see a practical guide to high-speed printed-circuit-board layout . power supply bypassing the ada4311-1 operates on supplies from 6 v to 12 v. the ada4311-1 circuit should be powered with a well-regulated power supply. careful attention must be paid to decoupling the power supply. high quality capacitors with low equivalent series resistance (esr), such as multilayer ceramic capacitors (mlccs), should be used to minimize supply voltage ripple and power dissipation. in addition, 0.1 f mlcc decoupling capacitors should be located no more than ?-inch away from each of the power supply pins. a large, usually tantalum, 10 f capacitor is required to provide good decoupling for lower frequency signals and to supply current for fast, large signal changes at the ada4311-1 outputs. bypassing capacitors should be laid out in such a manner as to keep return currents away from the inputs of the amplifiers, which minimizes any voltage drops that can develop due to ground currents flowing through the ground plane. a large ground plane also provides a low impedance path for the return currents.
ada4311-1 rev. 0 | page 13 of 16 outline dimensions * compliant to jedec standards mo-187-ba-t except for exposed pad dimensions. 073007-b 0.70 0.55 0.40 8 0 0.94 0.86 0.78 seating plane 1.10 max 0.15 0.10 0.05 0.30 0.23 0.15 5.05 4.90 4.75 * 2.27 2.17 2.07 * 1.83 1.73 1.63 3.10 3.00 2.90 3.10 3.00 2.90 10 6 5 1 0.50 bsc 0.50 bsc pin 1 indicator c oplanarity 0.10 0.23 0.18 0.13 top view bottom view exposed pa d figure 23. 10-lead mini small outline package with exposed pad [mini_so_ep] (rh-10-1) dimensions shown in millimeters ordering guide model temperature range package description package option branding ada4311-1arhz 1 ?40c to +85c 10-lead mini small outline package with exposed pad [mini_so_ep] rh-10-1 1a ada4311-1arhz-rl 1 ?40c to +85c 10-lead mini small outline package with exposed pad [mini_so_ep] rh-10-1 1a ada4311-1arhz-r7 1 ?40c to +85c 10-lead mini small outline package with exposed pad [mini_so_ep] rh-10-1 1a 1 z = rohs compliant part.
ada4311-1 rev. 0 | page 14 of 16 notes
ada4311-1 rev. 0 | page 15 of 16 notes
ada4311-1 rev. 0 | page 16 of 16 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06940-0-8/07(0)

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